The invention relates to methods and apparatuses for fabricating a metal layer on a substrate, and more particularly, to methods and apparatuses for depositing a metal layer on a substrate using electrochemical deposition (ECD).
Conventionally, conductive interconnections on integrated circuits take the form of trenches and vias. In modern deep submicron integrated circuits, the trenches and vias are typically formed by a damascene or dual damascene process. Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to its lower resistivity and better electromigration resistance. Electrochemical deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electroplating is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
FIG. 1 is a schematic view of a conventional apparatus for electrochemical plating 100, with a wafer 10 mounted onto a substrate holder assembly 110. The substrate holder assembly 110 is mounted on a rotatable spindle 120 which allows rotation thereof.
During electrochemical plating, the substrate holder assembly 110 as well as the wafer 10 are placed in a plating bath 130 containing plating solution. Typical electroplating solution contains electrolyte, such as CuSO4 and other additives.
A DC power supply 150 has a negative output lead electrically connected to wafer 10 through one or more contact rings (not shown). The positive output lead of power supply 150 is electrically connected to an anode 101 located in the plating bath 130. During electroplating, power supply 150 biases the wafer 10 to provide a negative potential relative to the anode 101 causing electrical current to flow from the anode 101 to the wafer 10. This causes an electrochemical reaction (e.g. Cu2++2e−=Cu) on the wafer 10 which results in deposition of the electrically conductive layer (e.g. copper) on the wafer 10. The ion concentration of the plating solution is replenished during the plating cycle, for example by dissolution of a metallic anode (e.g. Cu=Cu2++2e−).
Referring to FIG. 2, a conventional substrate holder assembly 110 comprises a substrate chuck 112 with the wafer 10 mounted thereon. A cathode contact ring 115, typically formed of metal such as platinum, electrically connects the wafer 10 to render a negative potential relative to the anode (not shown) causing electrical current to flow from the anode to the wafer 10.
However, since the cathode contact ring 115 is solid, under layers, such as a low-k dielectric layer, can tend to exhibit cracking 32 (FIG. 3A) and peeling 34 (FIG. 3B) after chemical mechanical polishing (CMP).
U.S. Pat. No. 6,635,157 (Dordi et. al.), the entirety of which is hereby incorporated by reference, describes a bladder assembly that provides pressure to the backside of a wafer and ensures electrical contact between the wafer plating surface and the cathode contact ring. However, the pressure between the electrical contact ring and the wafer plating surface are still quite large, and can cause cracking and peeling in the low-k dielectric layer.